1. Field
The present disclosure relates generally to methods and systems for production of electronic devices, and devices produced therefrom. More specifically, the present disclosure relates to methods and systems for production of circuits containing nanotubes.
2. Background
Modern processor chip designs often include one or more caches on the same integrated circuit chip as the processor, and in some cases include multiple processors on a single integrated circuit chip. Despite the enormous improvement in speed obtained from integrated circuitry, the demand for even faster computer systems has continued. With this demand comes a need for even further size reduction in the logic circuitry within an integrated circuit chip.
A typical integrated circuit chip is constructed in multiple layers. Many active and passive elements are formed on a substrate (usually silicon). A dielectric layer is placed over the elements, and multiple conductive layers, each separated by another dielectric layer, are formed over the elements. The conductive layers carry power and ground potentials, as well as numerous signal interconnects running among active elements. Each conductive layer comprises multiple discrete conductors, often running substantially in parallel. Conductive interconnects between conductive layers, or between a conductive layer and an active or passive element, are formed as holes in the dielectric layers, called vias, into which a conductive metal, such as aluminum or copper, is introduced.
The number of active elements in a typical processor dictates a very large number of interconnections, and since these must be packaged within a small area, the size of individual interconnections is limited. Conductors, whether in the conductive layer or the via between conductive layers, have a small, finite resistance, which grows as the cross-sectional area of the conductor shrinks. Increasing the number of logic elements on a chip requires a larger number of conductors, which in turn reduces the amount of space available for each individual conductor. If all other design parameters remain the same, this has the effect of increasing the resistances of the individual conductors.
Recently, carbon nanotubes have been used to form conductive pathways in integrated circuits. Carbon nanotubes are cylindrically structured carbon allotropes composed entirely of sp2-hybridized bonding between carbon atoms. A single walled carbon nanotube is conceptually a one-atom-thick layer of graphene wrapped into a seamless cylinder.
Manufacturing of carbon nanotube-based electronics requires the positioning of each individual nanotube, which is prohibitive in terms of time and cost. While carbon nanotube-based electronics can be fabricated, individual nanotubes must be directly placed to create the carbon nanotube-based electronics. The direct placement of nanotubes requires an atomic force microscopy tip or similar microscope tip to position each of the nanotubes to form each electrical connection. The required time and cost of manually positioning each of the nanotubes to form each electrical connection is prohibitive of production scale manufacturing of carbon nanotube-based electronics.
Therefore, it would be advantageous to have a method and apparatus that takes into account at least one of the issues discussed above, as well as possibly other issues.